1. Field of the Invention
The present invention is generally in the field of fabrication of structures in semiconductor chips. In particular, the invention is in the field of fabrication of structures using low dielectric constant (xe2x80x9clow-kxe2x80x9d) material.
2. Background Art
It is known in the art that a dielectric material used in the fabrication of integrated circuit structures should have a low dielectric constant (xe2x80x9clow-kxe2x80x9d). The advantages of using low dielectric constant material in such structures are well-known. One of the advantages is a reduction in the inter-line coupling capacitance between metal lines. Such capacitance causes xe2x80x9cnoisexe2x80x9d or xe2x80x9ccrosstalkxe2x80x9d between metal lines. Another advantage is the reduction of capacitance between different layers of interconnect and also a reduction of capacitance between a layer of interconnect to the substrate. It is known in the art that a lower capacitance will reduce the interconnect metal line delay, i.e. the xe2x80x9cRCxe2x80x9d delay. Another advantage is the significant decrease in power consumption resulting from the lower capacitance since the amount of power consumed is directly proportional to the capacitance. Thus, it is generally appreciated in the art that the use of low dielectric constant material in the fabrication of integrated circuit structures is desirable for the reasons mentioned above.
Silicon dioxide is one of the dielectric materials used in the fabrication of integrated circuit structures because of its desirable features such as adequate hardness, and ease of cleaning and etching for even small feature sizes. However, the dielectric constant value of silicon dioxide is about 4.0. It is generally appreciated in the art that this dielectric constant value is too high. Thus, there is a drive to utilize materials with lower dielectric constant values in the fabrication of integrated circuit structures.
Polymers with a dielectric constant value of 2.5 or 3.0 are achievable. One method of reducing the dielectric constant of some polymer films is to increase the porosity of the polymer by introducing air into the pores of the polymer. Since the dielectric constant value of air is 1.0, introducing air into the material decreases the dielectric constant value of the material.
However, there are also problems associated with the use of lower dielectric constant material in the fabrication of integrated circuit structures. For example, etching low-k dielectric is difficult. Most low-k dielectrics are easily damaged by the etch chemistry or plasma. As an example, hydrogen silsesquioxane (also referred to as xe2x80x9cHSQxe2x80x9d) is a low-k dielectric which has been used in the fabrication of integrated circuits. However, the silicon-hydrogen bond in hydrogen silsesquioxane is weak and can easily be broken. Once the silicon-hydrogen bond is broken, the remaining material exhibits a tendency to absorb moisture. Also, during etching of most low-k dielectrics, polymers are generated which are hard to clean without etching away the low-k dielectric itself.
In addition, most low-k dielectrics have poor mechanical strength. One reason poor mechanical strength is undesirable is because low-k dielectric may not withstand chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d). It is known in the art that the CMP process is usually used to remove excess metal over the wafer surface after the metal has been used to create damascene structures.
Thus, problems associated with the use of a low-k dielectric material in the fabrication of integrated circuit structures include (a) difficulty in etching and cleaning low-k dielectric materials; (b) undesirable absorption of moisture; and (c) low mechanical strength of low-k dielectric materials.
It is known that when dielectric material is exposed to electron beams (E-beams) or ion beams (I-beams), the properties of the dielectric material can be changed. For example, a paper entitled xe2x80x9cE-Beam Curing Process of Low-K Dielectrics for unlanded vias in 0.25 xcexcm CMOS Technologyxe2x80x9d by David Feiler, Q. Z. Liu, and Maureen R. Brongo discusses an E-beam curing process of low-k dielectrics for unlanded vias in a CMOS technology. It is shown in that paper that the properties of the low-k dielectric can be modified so as to prevent unlanded vias from penetrating too deeply into the underlying low-k dielectric.
A second paper entitled xe2x80x9cA Novel and Low Thermal Budget Planarization Scheme for Pre- and Inter-Metal Dielectric Using HSQ (Hydrogen Silsesquioxane) Based SOG with Electron-Beam Curing for 256 Mbit DRAM and Beyondxe2x80x9d by Juseon Goo, Hae-Jeong Lee, Seong Ho Kim, Ji Hyun Choi, Byung Keun Hwang, Ho-Kyu Kang, and Moon Yong Lee discusses a finding that hydrogen silsesquioxane can be cured and densified with exposure to E-beams.
A third paper entitled xe2x80x9cIntegration of Low k Spin-on Polymer (SOP) Using Electron Beam Cure for Non-Etch-Back Applicationxe2x80x9d by Jane C. M. Hui, Yi Xu, Chow Yeog Foong, Liao Marvin, Lin Charles, and Lin Yih Shung discusses an E-beam curing process for spin-on glass materials in relation to spin-on polymer non-etch-back processing such as xe2x80x9cvia poisoning.xe2x80x9d It is shown that after E-beam exposure, the tested materials"" properties had changed, e.g. lower moisture content, higher film density and higher resistance were achieved.
A fourth paper entitled xe2x80x9cEffects of Electron Beam Exposure on Poly(arylene Ether) Dielectric Filmsxe2x80x9d by J. S. Drage, J. J. Yang, D. K. Choi, R. Katsanes, K. S. Y. Lau, S.-Q. Wang, L. Forester, P. E. Schilling, and M. Ross discusses the effects of E-beam exposure on chemical and physical properties of an organic dielectric film. Specifically, solvent resistance, glass transition temperature, and dielectric constant of the film are studied. The results of the study indicate that E-beam curing does not raise the dielectric constant compared to thermally-cured film.
In addition to the above-discussed papers, there are patents utilizing methods that alter the physical properties of dielectric materials using ion implantation. One such patent is U.S. Pat. No. 5,496,776 entitled xe2x80x9cSpin-On Glass Planarization Process With Ion Implantation.xe2x80x9d This patent discloses a method for planarizing an integrated circuit surface with a spin-on-glass sandwich layer, where the entire surface area of spin-on-glass exposed within a via etched through the spin-on-glass sandwich layer is not susceptible to sorption and outgassing of moisture. The patent also teaches a method of planarizing an integrated circuit surface which does not result in metallurgy and high resistivity problems associated with metallic interconnections through vias etched through the planarizing layer. One step in these methods is the implantation of ions into and through a spin-on-glass layer under various conditions. This method eliminates the need for an etch back process for the spin-on-glass exposed within the etched vias prior to metal deposition into those etched vias.
U.S. Pat. No. 5,192,697 entitled xe2x80x9cSOG Curing By Ion Implantationxe2x80x9d discloses among other things, a method of curing the spin-on-glass layer of an article which results in similar or better dielectric strength than a temperature cure method. Ions, such as argon or arsenic are implanted into the spin-on-glass layer of an article. The action of the ions moving through the spin-on-glass layer causes heating. This heating cures the spin-on-glass layer of the article.
U.S. Pat. No. 5,413,953 entitled xe2x80x9cMethod Of Planarizing An Insulator On A Semiconductor Substrate Using Ion Implantationxe2x80x9d discloses an improved process for fabricating planar field oxide structures on a silicon substrate. The patent also discloses an improved process for fabricating planar Field Oxide (FOX) isolation structures and an improved process for fabricating planar insulating layers over patterned conducting layers by ion implantation and etching.
As part of these processes, the substrate surface is implanted with arsenic or phosphorus ions. This ion implantation results in a damaged oxide layer, which etches approximately 2 to 4 times faster than the undamaged portion of the field oxide. As a result of faster etching of the damaged portion of the field oxide, the desired structures can be more easily fabricated.
Although it is desirable to use low-k dielectrics for the reasons stated above, the use of low-k dielectrics is accompanied by various problems also discussed above. The above-discussed papers and patents have not overcome a number of problems associated with the use of low-k dielectrics. Accordingly, there is a need in the art for using low-k dielectric materials in the fabrication of integrated circuit structures while overcoming the various problems resulting from the use of low-k dielectric materials. For example, there is need to use low-k dielectric material in the recently developed damascene fabrication processes while overcoming the various problems resulting from the use of such material.
The present invention teaches fabrication of improved low-k dielectric structures. According to the present invention, low-k dielectric structures are fabricated while overcoming the otherwise existing problems associated with the use of low-k dielectric materials. The invention resolves the difficulties in etching and cleaning low-k dielectric materials, the undesirable absorption of moisture by low-k dielectric materials, and the low mechanical strength of low-k dielectric materials.
In one embodiment of the invention, the physical properties of a low-k dielectric material is modified by exposing the low-k dielectric material to electron beams. The exposed portion of the low-k dielectric material becomes easier to etch and clean and exhibits greater mechanical strength and a reduction in absorption of moisture. In another embodiment of the invention, a number of incremental exposure and etch steps are performed to fabricate a desired structure.
In yet another embodiment of the invention, the steps of exposure of a low-k dielectric material are combined with the etch steps. The exposure and the etching of the low-k dielectric material are performed concurrently in the same system. In still another embodiment, the invention utilizes a single exposure and a single etch step to fabricate a desired structure. All embodiments of the invention can be practiced by exposing the low-k dielectric material to ion beams instead of electron beams.